The present invention relates to the manufacture of integrated circuits (ICs). More particularly, the present invention relates to improved designs for integrated test pads that advantageously improve structural integrity and substantially minimize the level of particulate contamination during IC manufacturing.
In the fabrication of semiconductor integrated circuits, devices such as component transistors, resistors, capacitors, and the like are typically formed on a substrate, e.g., a silicon wafer. The substrate typically includes a plurality of layers, out of which semiconductor device components are formed, e.g., via etching, doping, or the like. After the desired circuits are formed on the wafer, the wafer may then be diced into a plurality of dies. The dies may then be packaged into the finished IC products.
To monitor the performance of the manufacturing process and/or test the quality of the semiconductor devices formed on the substrate, integrated conductive test pads, which may be formed by conventional semiconductor manufacturing processes (e.g., deposition and etching) may be provided on the substrate. The integrated test pads provide electrical paths to selected devices, thereby allowing their electrical parameters to be measured from externally, e.g., via test probes. By comparing the measured parameters against the designed parameters, the performance of the semiconductor manufacturing process(es) may be ascertained.
To facilitate discussion, FIG. 1 is a cross-sectional view of a greatly simplified layer stack 100, including an integrated resistor 102 which may be formed out of, for example, layer 104. Above layer 104, there is disposed a dielectric layer 110, which mechanically supports and electrically insulates test pads 106 and 108 from one another. To provide an electrical path between test pad 106 and integrated resistor 102, a conducting via 112 is employed to couple test pad 106 to one end of integrated resistor 102. Likewise, test pad 108 is coupled to the other end of integrated resistor 102 by a conducting via 114. In the example of FIG. 1, test pads 106 and 108 may be employed during quality control to, for example, test the resistivity of integrated resistor 102. The measured resistivity may be compared against the designed resistivity value to determine whether the process(es) employed to fabricate integrated resistor 102 performed as intended.
Layer stack 100, as mentioned, is greatly simplified to facilitate ease of understanding. In many cases, the test pads are not located directly above the device to be measured, e.g., resistor 102 in the above example. To maximize use of the available wafer area, the test pads may be located in the kerf regions of the wafer, i.e., the regions between adjacent dies. Multiple metallization layers may then be employed to facilitate the conduction of electrical signals from the interior region of the die to the kerf region, where the test pads are located. The top surface of a test pad is typically dimensioned such that the test pad can accommodate a probe contacting the test pad from above. If a 25 micron probe tip is employed, the top surface of test pad 106 may measure 100 microns by 100 microns, for example.
If test pads 106 and 108 were solid metal plates or solid metal plugs, the mechanical strength of the test pads is relatively high. However, the use of solid metal test pads may cause difficulties to the dicing operation that is employed to cut the wafer into dies after semiconductor processing is completed. As is known by those skilled in the art, it is preferable during dicing to minimize as much as possible any contact between the dicing blade and metal. Too much metal-to-blade contact can shorten the life of the dicing blade, necessitating frequent and expensive replacements. This is particularly true if test pads 106 and 108 are formed of a hard metal such as tungsten.
To minimize the amount of metal contact between the dicing blade and the test pads, there is proposed in the prior art a test pad design which consists of a plurality of substantially identically sized matrices of interconnected pads. These substantially identically sized matrices of interconnected pads are disposed atop one another, albeit separated from one another by a layer of dielectric material. To facilitate discussion, FIG. 2 illustrates a top view of matrix 202, representing a portion of a simplified prior art test pad in which pads 204 are interconnected by a plurality of pad connectors 206. Pads 204 and pad connectors 206 are typically formed out of a single layer of metal, e.g., etched out of a blanket deposited metal layer such as an aluminum layer. Tungsten is sometimes employed as well. Pad 204 may measure, in a prior art example, about 2.4 microns by 2.4 microns. Pad connector 206 may measure, in a prior art example, about 2.4 microns by 0.9 micron.
A subsequently deposited oxide layer, in addition to providing a dielectric insulating layer above matrix 202, fills in the interstitial spaces between the pads. Compared to a solid metal plate of a similar size, the matrix structure of matrix 202 has less metal within the test pad, thereby reducing the amount of metal-to-blade contact should the dicing blade need to slice through matrix 202 when the wafer is cut up into dies.
When multiple matrices are involved, the prior art approach has been to provide substantially similar matrices 102 in the multiple metal levels, and to interconnect the matrices together using conductive vias through the dielectric interlayers. FIG. 3 is a cross sectional view of a prior art test pad 302 in which multiple identical matrices 202 are essentially stack on top of one another, albeit separated from one another by a dielectric layer 304. A plurality of conductive vias 306 are shown coupling matrix 202a with matrices 202b and 202c through dielectric layers 304a and 304b. One skilled in the art would readily recognize that prior art test pad 302 employs less metal in its construction than one that is solid. As mentioned earlier, the reduced amount of metal within the test pad minimizes the amount of metal-to-blade contact when the wafer is diced.
When prior art test pad 302 of FIG. 3 is employed in the manufacture of certain circuits, e.g., Dynamic Random Access Memory (DRAM), it has been found to be deficient in certain areas. For example, DRAM manufacturing often employs a TV etch, followed by a crack stop etch (CSE). TV etch consists of a blanket RIE (reactive ion etching) removal of oxide that is not masked by a metal or polyimide layer. Crack stop etch (CSE) consists of an etch of the exposed metal (e.g., a peroxide or H.sub.2 O.sub.2 etch of tungsten).
With reference to FIG. 2, the TV etch attacks the open oxide areas adjacent to a pad, e.g., open areas 208a-d surrounding pad 204a. The TV etch, which is a dry etch, typically forms fairly isotropic etch features. Accordingly, some of the edges of pad 204a, as well as the pad connectors 206 that are adjacent to it, may be exposed after the TV etch. If the TV etch is of a sufficiently long duration, it may be deep enough to even expose the edges of the pads and pad connectors in the matrix at the lowest level of the test pad. Typically, this bottom matrix layer is formed of tungsten. The subsequent crack stop etch then attacks the pads and pad connectors, which have been stripped off their protective oxide covering by the earlier TV etch.
The inadvertent etching of the underlying tungsten pads may lead to many problems. If enough of the underlying tungsten is attacked, test pad 302 may become unstable and/or poorly supported mechanically. For example, some of pads 204 in the upper level matrices may be delaminated and become particulate contaminants, which may contaminate the wafer during subsequent processing steps and lead to reliability problems. Further, the removal of oxide undermines the structural integrity of test pad 302, causing some prior art test pad 302 to collapse when the test probe is applied to its top surface. Additionally, the lack of structural integrity and/or delamination may cause some of pads 204 of the prior art test pad to disintegrate, either on their own or when coming into contact with the dicing blade, thereby increasing the level of contaminants on the substrate, leading to even more severe quality control problems.
In view of the foregoing, there are desired improved test pad designs, and methods therefor, which advantageously increase the integrity of the test pads as well as minimize contamination to the substrate even after the test pads are subject to the TV and/or crack stop etches.